SPLASH 2022
Mon 5 - Sat 10 December 2022 Auckland, New Zealand
Sat 10 Dec 2022 11:30 - 12:00 at AMRF Auditorium - Logic and Concurrency Chair(s): Mohsen Lesani

Transactional memory (TM) is an intensively studied synchronisation paradigm with many proposed implementations in software and hardware, and combinations thereof. However, TM under relaxed memory, e.g., C11 (the 2011 C/C++ standard) is still poorly understood, lacking rigorous foundations that support verifiable implementations. This paper addresses this gap by developing TMS2-ra, a relaxed operational TM specification. We integrate TMS2-ra with RC11 (the repaired C11 memory model that disallows load-buffering) to provide a formal semantics for TM libraries and their clients. We develop a logic, TARO, for verifying client programs that use TMS2-ra for synchronisation. We also show how TMS2-ra can be implemented by a C11 library, TML-ra, that uses relaxed and release-acquire atomics, yet guarantees the synchronisation properties required by TMS2-ra. We benchmark TML-ra and show that it outperforms its sequentially consistent counterpart in the STAMP benchmarks. Finally, we use a simulation-based verification technique to prove correctness of TML-ra. Our entire development is supported by the Isabelle/HOL proof assistant.

Sat 10 Dec

Displayed time zone: Auckland, Wellington change

10:30 - 12:00
Logic and ConcurrencyOOPSLA at AMRF Auditorium
Chair(s): Mohsen Lesani University of California at Riverside
10:30
30m
Talk
A Concurrent Program Logic with a Future and History
OOPSLA
Roland Meyer TU Braunschweig, Thomas Wies New York University, Sebastian Wolff New York University
DOI
11:00
30m
Talk
CAAT: Consistency as a TheoryDistinguished Paper
OOPSLA
Thomas Haas TU Braunschweig, Roland Meyer TU Braunschweig, Hernán Ponce de León Huawei Dresden Research Center
DOI
11:30
30m
Talk
Implementing and Verifying Release-Acquire Transactional Memory in C11
OOPSLA
Sadegh Dalvandi University of Surrey, Brijesh Dongol University of Surrey
DOI